Graph Sparsification Approach to Scalable Parallel SPICE-Accurate Simulation of Post-layout Integrated Circuits

Researcher: Zhuo Feng, PI, Associate Professor, Electrical and Computer Engineering

Sponsor: National Science Foundation: SHF: Small

Amount of Support: $250,701

Duration of Support: 4 years

Abstract: Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for design and verification of nanoscale ICs. However, for post-layout nanoscale circuits, using traditional SPICE-accurate simulation techniques to encapsulate multi-million or even multi-billion devices coupled through complex parasitics can be prohibitively expensive, and thus not applicable to large IC designs, since the runtime and memory cost for solving large sparse matrix problems using direct solution methods will increase quickly with the growing circuit sizes and parasitics densities. To achieve greater simulation efficiency and capacity during post-layout simulations, preconditioned iterative solution techniques have been recently proposed to substitute the direct solution methods. However, existing preconditioned methods for post-layout circuit simulations are typically designed with various assumptions and constraints on the circuit and systems to be analyzed, which therefore cannot be effectively and reliably applied to general-purpose SPICE-accurate circuit simulations. In this research project, the PI will study efficient yet robust circuit-oriented preconditioning approaches for scalable SPICE-accurate post-layout IC simulations by leveraging recent graph sparsification research. By systematically sparsifying linear/nonlinear dynamic networks originated from dense parasitics components and complex device elements of post-layout circuits, scalable, and more importantly, parallelizable preconditioned iterative algorithms will be investigated and developed by the PI to enable much greater speed and capacity for SPICE-accurate IC simulations in both time and frequency domains.

The successful completion of this work will immediately benefit the semiconductor industries. The algorithms and methodologies to be developed through this project will be integrated into undergraduate/graduate level VLSI design/CAD courses, while the research results will be broadly disseminated to major semiconductor and EDA companies for potential industrial applications. The CAD tools developed under this research plan will also be exchanged with collaborating industrial partners. The acquired experience in the proposed research plan is also likely to contribute to computing advances in other science and engineering fields, impacting broader research areas that are related to large/complex system modeling and simulation.

Publications:

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI:10.1109/TCAD.2014.2376991

Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI: 10.1109/TCAD.2015.2424958

Zhuo Feng. “Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014. doi:DOI: 10.1109/TVLSI.2013.2290104

Xueqian Zhao, Lengfei Han, and Zhuo Feng . “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations. ,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., 2015.

Zhuo Feng. “Spectral Graph Sparsification in Nearly-Linear Time Leveraging Efficient Spectral Perturbation Analysis,” ACM/IEEE Design Automation Conference, 2016.

Lengfei Han, and Zhuo Feng. “Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems,” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2015.

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Efficient Graph Sparsification Approach to Scalable Harmonic Balance (HB) Analysis of Strongly Nonlinear RF Circuits,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013.

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Xueqian Zhao, Zhuo Feng, and Zhuo Cheng. “An Efficient Spectral Graph Sparsification Approach to Scalable Reduction of Large Flip-Chip Power Grids,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.

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