Archives—July 2019

Susanta Ghosh is PI on $170K NSF Grant

Susanta Ghosh

Susanta Ghosh (ICC-DataS/MEEM/MuSTI) is Principal Investigator on a project that has received a $170,604 research and development grant from the National Science Foundation. The project is titled “EAGER: An Atomistic-Continuum Formulation for the Mechanics of Monolayer Transition Metal Dichalcogenides.” This is a potential 19-month project.

Dr. Ghosh is an assistant professor of Mechanical Engineering-Engineering Mechanics at Michigan Tech. Before joining the Michigan Tech College pof Engineering, Dr. Ghosh was an associate in research in the Pratt School of Engineering at Duke University; a postdoctoral scholar in the departments of Aerospace Engineering and Materials Science & Engineering at the University of Michigan, Ann Arbor; and a research fellow at the Technical University of Catalunya, Barcelona, Spain. His M.S. and Ph.D. degrees are from the Indian Institute of Science (IISc), Bangalore. His research interests include multi-scale solid mechanics, atomistic modeling, ultrasound elastography, and inverse problem and computational science.

Abstract: Two-dimensional materials are made of chemical elements or compounds of elements while maintaining a single atomic layer crystalline structure. Two-dimensional materials, especially Transition Metal Dichalcogenides (TMDs), have shown tremendous promise to be transformed into advanced material systems and devices, e.g., field-effect transistors, solar cells, photodetectors, fuel cells, sensors, and transparent flexible displays. To achieve broader use of TMDs across cutting-edge applications, complex deformations for large-area TMDs must be better understood. Large-area TMDs can be simulated and analyzed through predictive modeling, a capability that is currently lacking. This EArly-concept Grant for Exploratory Research (EAGER) award supports fundamental research that overcomes current challenges in large-scale atomistic modeling to obtain an efficient but reliable continuum model for single-layer TMDs containing billions of atoms. The model will be translational and will contribute towards the development of a wide range of applications in the nanotechnology, electronics, and alternative energy industries. The award will further support development of an advanced graduate-level course on multiscale modeling and organization of symposia in two international conferences on mechanics of two-dimensional materials. Experimental samples of TMDs contain billions of atoms and hence are inaccessible to the state-of-the-art molecular dynamics simulations. Moreover, existing crystal elastic models for surfaces cannot be applied to multi-atom thick 2D TMDs due to the presence of interatomic bonds across the atomic surfaces. The crystal elastic model aims to solve this problem by projecting all interatomic bonds onto the mid-surface to track their deformations. The actual deformed bonds will, therefore, be computed using the deformations of the mid-surface. Additionally, a technique will be derived to incorporate the effects of curvature and stretching of TMDs on their interactions with substrates. The model will be exercised to generate insights into the mechanical instabilities and the role of substrate interactions on them. The coarse-grained model will overcome the computational bottleneck of molecular dynamics models to simulate TMDs samples comprising billions of atoms. This award reflects NSF’s statutory mission and has been deemed worthy of support through evaluation using the Foundation’s intellectual merit and broader impacts review criteria.



Bo Chen is PI of $200K NSF Research and Development Grant

Bo Chen (CS/CyberS) is Principal Investigator on a project that has received a $199,975 research and development grant from the National Science Foundation. The project is titled “EAGER: Enabling Secure Data Recovery for Mobile Devices Against Malicious Attacks.” This is a potential two-year project.

Abstract: Mainstream mobile computing devices like smart phones and tablets currently rely on remote backups for data recovery upon failures. For example, an iPhone periodically stores a recent snapshot to iCloud, and can get restored if needed. Such a commonly used “off-device” backup mechanism, however, suffers from a fundamental limitation that, the backup in the remote server is not always synchronized with data stored in the local device. Therefore, when a mobile device suffers from a malware attack, it can only be restored to a historical state using the remote backup, rather than the exact state right before the attack occurs. Data are extremely valuable for both organizations and individuals, and thus after the malware attack, it is of paramount importance to restore the data to the exact point (i.e., the corruption point) right before they are corrupted. This, however, is a challenging problem. The project addresses this problem in mobile devices and its outcome could benefit billions of mobile users.

A primary goal of the project is to enable recovery of mobile devices to the corruption point after malware attacks. The malware being considered is the OS-level malware which can compromise the OS and obtain the OS-level privilege. To achieve this goal, the project combines both the traditional off-device data recovery and a novel in-device data recovery. Especially, the following research activities are undertaken: 1) Designing a novel malware detector which runs in flash translation layer (FTL), a firmware layer staying between OS and flash memory hardware. The FTL-based malware detector ensures that data being committed to the remote server will not be tampered with by the OS-level malware. 2) Developing a novel approach which ensures that the OS-level malware is not able to corrupt data changes (i.e., delta) which have not yet been committed to the remote server. This is achieved by hiding the delta in the flash memory using flash storage’s special hardware features, i.e., out-of-place update and strong physical isolation. 3) Developing a user-friendly approach which can allow users to conveniently and efficiently retrieve the delta hidden in the flash memory for data recovery after malware attacks.

Link to an Unscripted article about related research at  https://www.mtu.edu/unscripted/stories/2018/march/how-to-speed-up-bare-metal-malware-analysis-and-better-protect-mobile-devices.html.


Ali Ebnenasir is Co-Author of Publication in ACM Transactions on Computational Logic

Ali Ebnenasir

An article co-authored by Ali Ebnenasir (SAS/CS) and Alex Klinkhamer, “Verification of Livelock-Freedom and Self-Stabilization on Parameterized Rings,” was recently published in ACM Transactions on Computational Logic.

Abstract: This article investigates the verification of livelock-freedom and self-stabilization on parameterized rings consisting of symmetric, constant space, deterministic, and self-disabling processes. The results of this article have a significant impact on several fields, including scalable distributed systems, resilient and self-* systems, and verification of parameterized systems. First, we identify necessary and sufficient local conditions for the existence of global livelocks in parameterized unidirectional rings with unbounded (but finite) number of processes under the interleaving semantics. Using a reduction from the periodic domino problem, we show that, in general, verifying livelock-freedom of parameterized unidirectional rings is undecidable (specifically, Π10-complete) even for constant space, deterministic, and self-disabling processes. This result implies that verifying self-stabilization for parameterized rings of self-disabling processes is also undecidable. We also show that verifying livelock-freedom and self-stabilization remain undecidable under (1) synchronous execution semantics, (2) the FIFO consistency model, and (3) any scheduling policy. We then present a new scope-based method for detecting and constructing livelocks in parameterized rings. The proposed semi-algorithm behind our scope-based verification is based on a novel paradigm for the detection of livelocks that totally circumvents state space exploration. Our experimental results on an implementation of the proposed semi-algorithm are very promising as we have found livelocks in parameterized rings in a few microseconds on a regular laptop. The results of this article have significant implications for scalable distributed systems with cyclic topologies.

https://dl.acm.org/citation.cfm?id=3326456&dl=ACM&coll=DL

doi: 10.1145/3326456


DARPA Research Mentioned in AI Magazine Article

Shane Mueller

This month’s AI magazine includes the article “DARPA’s Explainable Artificial Intelligence Program,” which mentions Michigan Tech’s DARPA research. ICC member Shane Mueller is principal investigator of a 4-year, $255K DARPA XAI project.

The section of the article “Naturalistic Decision-Making Foundations of XAI” reads: “The objective of the IHMC team (which includes researchers from MacroCognition and Michigan Technological University) is to develop and evaluate psychologically plausible models of explanation and develop actionable concepts, methods, measures, and metrics for explanatory reasoning. The IHMC team is investigating the nature of explanation itself.”

Abstract: Dramatic success in machine learning has led to a new wave of AI applications (for example, transportation, security, medicine, finance, defense) that offer tremendous benefits but cannot explain their decisions and actions to human users. DARPA’s explainable artificial intelligence (XAI) program endeavors to create AI systems whose learned models and decisions can be understood and appropriately trusted by end users. Realizing this goal requires methods for learning more explainable models, designing effective explanation interfaces, and understanding the psychologic requirements for effective explanations. The XAI developer teams are addressing the first two challenges by creating ML techniques and developing principles, strategies, and human-computer interaction techniques for generating effective explanations. Another XAI team is addressing the third challenge by summarizing, extending, and applying psychologic theories of explanation to help the XAI evaluator define a suitable evaluation framework, which the developer teams will use to test their systems. The XAI teams completed the first of this 4-year program in May 2018. In a series of ongoing evaluations, the developer teams are assessing how well their XAM systems’ explanations improve user understanding, user trust, and user task performance.

https://www.aaai.org/ojs/index.php/aimagazine/article/view/2850

https://doi.org/10.1609/aimag.v40i2.2850


Integrated Research and Education in Physical Design Automation for Nanotechnology and VLSI Technology Co-Design

Researcher: Shiyan Hu, PI, Adjunct Professor, Electrical and Computer Engineering

Sponsor: National Science Foundation

Amount of Support: $222,315

Duration of Support: 4 years

Abstract: This CAREER proposal aims to develop innovative chip layout design and optimization methodologies on nanotechnology interconnect and copper interconnect co-design. As the copper interconnect technology is approaching its fundamental physical limit, novel on-chip interconnect materials such as carbon nanotubes and graphene nano-ribbons have emerged as promising replacement materials due to properties such as superior conductivity and resilience to electromigration that otherwise have plagued copper interconnects. On the other hand, there could also be some issues for using nanotechnology interconnects such as their inferior performance as local interconnect and defects in fabrication. The PI will develop a novel co-design methodology which judiciously integrates nanotechnology into the practical VLSI circuit design together with various enabling techniques on co-design-aware buffering, layer assignment, routing, placement and clocking. The PI also proposes defect-aware techniques for mitigating the impacts due to defects, and improving robustness against faults for nanotechnology interconnects.

The broader impact of the proposed research is to significantly improve the circuit performance of nanoscale circuits. As the interconnect delay is the dominating factor of the circuit delay, the proposed research has the potential to help achieve the design closure for those difficult circuits whose timing cannot be closed even if various traditional physical synthesis optimizations have been stretched to the maximum extent. The proposed research can contribute integrated circuit design methodologies which enable the utilization of nanotechnologies into practical circuit design to defeat the fundamental limit on the prevailing VLSI technology. The PI will also develop a seamless integration of research with education such as developing the new graduate level course, developing lecture series and seminars, recruiting under-represented students, and showcasing the research results at conferences.

Publications:

Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, and Weikang Qian. “Timing-Driven Placement for Carbon Nanotube Circuits,” in Proceedings of IEEE International System-on-Chip Conference (SOCC), 2015, 2015.

Lin Liu, Yuchen Zhou and Shiyan Hu. “Buffering Carbon Nanotube Interconnects for Timing Optimization,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014.

Jia Wang, Lin Liu, Yuchen Zhou, and Shiyan Hu. “Buffering Carbon Nanotube Interconnects Considering Inductive Effects,” Journal of Circuits, Systems and Computers (JCSC), v.25, 2016.

Yang Liu, Lin Liu, Yuchen Zhou, and Shiyan Hu. “Leveraging Carbon Nanotube Technologies in Developing Physically Unclonable Function for Cyber-Physical System Authentication,” in Proceedings of IEEE INFOCOM Cyber-Physical System Security Workshop, 2016.

Jacob Wurm, Yier Jin, Yang Liu, Shiyan Hu, Kenneth Heffner, Fahim Rahman, Mark Tehranipoor. “Introduction to Cyber-Physical System Security: A Cross-Layer Perspective,” IEEE Transactions on Multi-Scale Computing Systems, v.3, 2017, p. 215-227.

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VACCS – Visualization and Analysis for C Code Security

Researchers:

Jean Mayo, PI, Associate Professor, Computer Science

Ching-Kuang Shene, co-PI, Professor, Computer Science

Sponsor: National Science Foundation

Amount of Support: $130,001

Duration of Support: 3 years

Abstract: The proposed project will develop Visualization and Analysis of C Code Security (VACCS) tool to assist students with learning secure code programming. The proposal addresses the critical issue of learning secure coding through the development of a system for analyzing and visualizing C code and associated learning materials. VACCS will utilize static and dynamic program analysis to detect security vulnerabilities and warn programmers about the potential errors in their code. The research team has a significant experience in using visualization to teach computer science in such areas as parallel computing, geometric modeling and data encryption. The project will develop visualization and animation of common security vulnerabilities that can be customized for programmers with different level of programming experience. The project will evaluate the effectiveness of VACCS and instructional materials to improve students’ learning of secure coding.

The outcomes of this research will provide a better understanding of the visualization impact on secure programming instruction within a computing curriculum, as well as a deployable VACCS tool for faculty to adopt. This research will inform the broader community on the visualization potential for positive effects on the quality of code developed by future computer scientists. The VACCS tool and educational materials including tutorials, lectures, projects and extensive examples of teaching secure software development will be disseminated to academic computing community. In addition, this project will teach students how to perform software security audits using VACCS and will train graduate students in the art of teaching computer security.

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Leveraging Heterogeneous Manycore Systems for Scalable Modeling, Simulation and Verification of Nanoscale Integrated Circuits

Researcher: Zhuo Feng, PI, Associate Professor, Electrical and Computer Engineering

Sponsor: National Science Foundation

Amount of Support: $400,000

Duration of Support: 6 years

Abstract: The goal of this CAREER research project is to best unleash the power of emerging heterogeneous manycore CPU-GPU computing platforms. This will require revolutionizing the next-generation Electronic Design Automation (EDA) tools to deal with unprecedented complexity of circuits involving billions of components, making possible their modeling, analysis and verification tasks which would be prohibitively expensive and even intractable with methods in use today. The experience acquired in this research is also likely to contribute to advances in the use of computing in other areas of science and engineering, thus impacting areas such as complex system modeling and simulation, computational fluid dynamics, social computing, and systems biology. The PI will promote undergraduate and underrepresented student research, as well as K-12 education outreach, to motivate students in pursuing advanced engineering education or a career in STEM areas. Additionally, the PI will integrate the research outcomes into undergraduate and graduate curriculum development, and leverage interdisciplinary, industrial and international collaborations to effectively facilitate the proposed research work and broadly disseminate the results. Future nanoscale Integrated Circuit (IC) subsystems, such as clock distributions, power delivery networks, embedded memory arrays, as well as analog and mixed-signal systems, may reach an unprecedented complexity involving billions of circuit components, making their modeling, analysis and verification tasks prohibitively expensive and intractable with existing EDA tools. On the other hand, emerging heterogeneous manycore computing systems, such as the manycore CPU-GPU computing platforms that integrate a few large yet power-consuming general purpose processors with massive number of much slimmer but more energy-efficient graphics processors, can theoretically delivery teraflops of computing power. The proposal aims to accelerate a paradigm shift in EDA research to more energy-efficient heterogeneous computing regimes. Towards this end, the PI will develop systematic hardware/software approaches to achieve scalable integrated circuit modeling, simulation and verifications by inventing heterogeneous CAD algorithms and data structures, as well as exploiting hardware-specific and domain-specific runtime performance modeling and optimization approaches.

Publications:

Xueqian Zhao*, Lengfei Han*, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Lengfei Han and Zhuo Feng. “Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems,” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2015.

Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Lengfei Han and Zhuo Feng. “TinySPICE Plus: Scaling Up Statistical SPICE Simulations on GPU Leveraging Shared-Memory Based Sparse Matrix Solution Techniques,” IEEE/ACM International Conference on Computer-Aided Design, 2016.

Zhuo Feng. “Spectral Graph Sparsification in Nearly-Linear Time Leveraging Efficient Spectral Perturbation Analysis,” ACM/IEEE Design Automation Conference, 2016.

Zhiqiang Zhao, Yongyu Wang, and Zhuo Feng. “SAMG: Sparsified Algebraic Multigrid for Solving Large Symmetric Diagonally Dominant (SDD) Matrices,” IEEE/ACM International Conference on Computer-Aided Design, 2017.

Zhiqiang Zhao, Zhuo Feng. “A Spectral Graph Sparsication Approach to Scalable Vectorless Power Grid Integrity Verication,” ACM/IEEE Design Automation Conference (DAC), 2017.

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Graph Sparsification Approach to Scalable Parallel SPICE-Accurate Simulation of Post-layout Integrated Circuits

Researcher: Zhuo Feng, PI, Associate Professor, Electrical and Computer Engineering

Sponsor: National Science Foundation: SHF: Small

Amount of Support: $250,701

Duration of Support: 4 years

Abstract: Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for design and verification of nanoscale ICs. However, for post-layout nanoscale circuits, using traditional SPICE-accurate simulation techniques to encapsulate multi-million or even multi-billion devices coupled through complex parasitics can be prohibitively expensive, and thus not applicable to large IC designs, since the runtime and memory cost for solving large sparse matrix problems using direct solution methods will increase quickly with the growing circuit sizes and parasitics densities. To achieve greater simulation efficiency and capacity during post-layout simulations, preconditioned iterative solution techniques have been recently proposed to substitute the direct solution methods. However, existing preconditioned methods for post-layout circuit simulations are typically designed with various assumptions and constraints on the circuit and systems to be analyzed, which therefore cannot be effectively and reliably applied to general-purpose SPICE-accurate circuit simulations. In this research project, the PI will study efficient yet robust circuit-oriented preconditioning approaches for scalable SPICE-accurate post-layout IC simulations by leveraging recent graph sparsification research. By systematically sparsifying linear/nonlinear dynamic networks originated from dense parasitics components and complex device elements of post-layout circuits, scalable, and more importantly, parallelizable preconditioned iterative algorithms will be investigated and developed by the PI to enable much greater speed and capacity for SPICE-accurate IC simulations in both time and frequency domains.

The successful completion of this work will immediately benefit the semiconductor industries. The algorithms and methodologies to be developed through this project will be integrated into undergraduate/graduate level VLSI design/CAD courses, while the research results will be broadly disseminated to major semiconductor and EDA companies for potential industrial applications. The CAD tools developed under this research plan will also be exchanged with collaborating industrial partners. The acquired experience in the proposed research plan is also likely to contribute to computing advances in other science and engineering fields, impacting broader research areas that are related to large/complex system modeling and simulation.

Publications:

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI:10.1109/TCAD.2014.2376991

Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI: 10.1109/TCAD.2015.2424958

Zhuo Feng. “Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014. doi:DOI: 10.1109/TVLSI.2013.2290104

Xueqian Zhao, Lengfei Han, and Zhuo Feng . “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations. ,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., 2015.

Zhuo Feng. “Spectral Graph Sparsification in Nearly-Linear Time Leveraging Efficient Spectral Perturbation Analysis,” ACM/IEEE Design Automation Conference, 2016.

Lengfei Han, and Zhuo Feng. “Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems,” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2015.

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Efficient Graph Sparsification Approach to Scalable Harmonic Balance (HB) Analysis of Strongly Nonlinear RF Circuits,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013.

Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

Xueqian Zhao, Zhuo Feng, and Zhuo Cheng. “An Efficient Spectral Graph Sparsification Approach to Scalable Reduction of Large Flip-Chip Power Grids,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.

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Effective Sampling-Based Miss Ratio Curves: Theory and Practice

Circuit board

Researcher: Zhenlin Wang, PI, Professor, Computer Science

Sponsor: National Science Foundation

Amount of Support: $390,876

Duration of Support: 4 years

Abstract: Caches, such as distributed in-memory cache for key-value store, often play a key role in overall system performance. Miss ratio curves (MRCs) that relate cache miss ratio to cache size are an effective tool for cache management. This project develops a new cache locality theory that can significantly reduce the time and space overhead of MRC construction and thus makes it suitable for online profiling. The research will influence system design in both software and hardware, as nearly every system involves multiple types of cache. The results can thus benefit a wide range of systems from personal desktops to large scale data centers. We will integrate our results into existing open source infrastructure for the industry to adopt. In addition, this project will offer new course materials that motivate core computer science research and practice.

The project investigates a new cache locality theory, applies it to several caching or memory management systems, and examines the impact of different online random sampling techniques. The theory introduces a concept of average eviction time that facilitates modeling data movement in cache. The new model constructs MRCs with data reuse distribution that can be effectively sampled. This model yields a constant space overhead and linear time complexity. The research is focused on theoretical properties and limitations of this model when compared with other recent MRC models. With this lightweight model, the project seeks to guide hardware cache partitioning, improve memory demand prediction and management in a virtualized system, and optimize key-value memory cache allocation.

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