PhD student Yuchen Wang, Computer Science, will present their final oral examination (defense) on Tuesday, July 16, 2024, at 9 am in Rekhi 101 and via Zoom online meeting.
The title of Wang’s defense is, “Dynamic Memory Management for Key-Value Store.”
Defense Abstract
To reduce the latency of accessing back-end servers, today’s web services commonly adopt in-memory key-value (k-v) stores at the front end to cache frequently accessed objects. Given the limited size of memory, these stores need to be configured with a fixed amount of memory, necessitating cache replacement when the footprint of accessed objects exceeds the cache size.
This thesis presents a comprehensive exploration of advanced dynamic memory management techniques for k-v stores. The first study conducts a detailed analysis of K-LRU, a random sampling-based replacement policy, proposing a dynamic K configuration scheme to exploit the potential miss ratio gap among various Ks. Experimental results demonstrate a throughput improvement of up to 32.5% over the default static K setting.
Building on this, the second study extends the exploration of K-LRU to a multi-tenant k-v store environment, introducing a locality- and latency-aware memory partitioning scheme. This approach significantly enhances performance, achieving up to a 50.2% reduction in average access latency and a 262.8\% increase in throughput compared to standard Redis. When compared to a state-of-the-art memory allocation design, the proposed scheme shows improvements of up to 24.8% in average access latency and 61.8\% in throughput.
Finally, inspired by emerging Compute Express Link (CXL) memory-sharing techniques, the third study pushes k-v store memory management into a multi-tier memory environment. This involves designing a software-defined tiered memory management architecture on top of a CXL memory-sharing switch. By dynamically identifying hot application data, efficiently migrating items among memory tiers based on popularity, and implementing multi-tenant memory partitioning, the proposed sdTMM system effectively integrates fast local DRAM with slower but larger CXL-shared memory. Evaluations across various workloads show that, even with 80% of the fast memory replaced by CXL-shared slow memory, sdTMM maintains a performance impact as low as 2.2% compared to an all-fast memory over-provisioned system.
This research collectively advances the techniques of dynamic memory management, demonstrating promising performance improvements in k-v stores.