Scott Pomerville, Computer Science, will present his PhD final oral examination (PhD defense) on Thursday, August 1, 2024, at 9 am in Rehki 101 and via Zoom online meeting.
The title of Pomerville’s defense is, “Statically Controlled Synchronized Lane Architectures.”
Defense Abstract
Modern superscalar processors dominate the field of computing. While dynamic execution allows for versatility in code, these processors are complex. Statically scheduled code has historically enabled simpler processor designs, static scheduling cannot account for variables that are unknown at compile time. Furthermore, static scheduling has many inefficiencies, such as the need to insert a large number of nops for code in traditional Very Long Instruction Word (VLIW) processors. In this dissertation, we explore a novel architectural approach for statically scheduled code by breaking the code into several synchronous instruction streams. By representing code in a fundamentally new way, we demonstrate that we can create robust processors that can handle dynamic levels of instruction level parallelism (ILP), and demonstrate the potential it has to target traditional weaknesses statically scheduled processors have had to deal with. This dissertation is an exploration of the consequences of allowing for multiple instruction streams, and possibilities opened up by changing program representation to allow for several simultaneous streams of instructions.