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    Integrated Research and Education in Physical Design Automation for Nanotechnology and VLSI Technology Co-Design

    Researcher: Shiyan Hu, PI, Adjunct Professor, Electrical and Computer Engineering

    Sponsor: National Science Foundation

    Amount of Support: $222,315

    Duration of Support: 4 years

    Abstract: This CAREER proposal aims to develop innovative chip layout design and optimization methodologies on nanotechnology interconnect and copper interconnect co-design. As the copper interconnect technology is approaching its fundamental physical limit, novel on-chip interconnect materials such as carbon nanotubes and graphene nano-ribbons have emerged as promising replacement materials due to properties such as superior conductivity and resilience to electromigration that otherwise have plagued copper interconnects. On the other hand, there could also be some issues for using nanotechnology interconnects such as their inferior performance as local interconnect and defects in fabrication. The PI will develop a novel co-design methodology which judiciously integrates nanotechnology into the practical VLSI circuit design together with various enabling techniques on co-design-aware buffering, layer assignment, routing, placement and clocking. The PI also proposes defect-aware techniques for mitigating the impacts due to defects, and improving robustness against faults for nanotechnology interconnects.

    The broader impact of the proposed research is to significantly improve the circuit performance of nanoscale circuits. As the interconnect delay is the dominating factor of the circuit delay, the proposed research has the potential to help achieve the design closure for those difficult circuits whose timing cannot be closed even if various traditional physical synthesis optimizations have been stretched to the maximum extent. The proposed research can contribute integrated circuit design methodologies which enable the utilization of nanotechnologies into practical circuit design to defeat the fundamental limit on the prevailing VLSI technology. The PI will also develop a seamless integration of research with education such as developing the new graduate level course, developing lecture series and seminars, recruiting under-represented students, and showcasing the research results at conferences.

    Publications:

    Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, and Weikang Qian. “Timing-Driven Placement for Carbon Nanotube Circuits,” in Proceedings of IEEE International System-on-Chip Conference (SOCC), 2015, 2015.

    Lin Liu, Yuchen Zhou and Shiyan Hu. “Buffering Carbon Nanotube Interconnects for Timing Optimization,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014.

    Jia Wang, Lin Liu, Yuchen Zhou, and Shiyan Hu. “Buffering Carbon Nanotube Interconnects Considering Inductive Effects,” Journal of Circuits, Systems and Computers (JCSC), v.25, 2016.

    Yang Liu, Lin Liu, Yuchen Zhou, and Shiyan Hu. “Leveraging Carbon Nanotube Technologies in Developing Physically Unclonable Function for Cyber-Physical System Authentication,” in Proceedings of IEEE INFOCOM Cyber-Physical System Security Workshop, 2016.

    Jacob Wurm, Yier Jin, Yang Liu, Shiyan Hu, Kenneth Heffner, Fahim Rahman, Mark Tehranipoor. “Introduction to Cyber-Physical System Security: A Cross-Layer Perspective,” IEEE Transactions on Multi-Scale Computing Systems, v.3, 2017, p. 215-227.

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    VACCS – Visualization and Analysis for C Code Security

    Researchers:

    Jean Mayo, PI, Associate Professor, Computer Science

    Ching-Kuang Shene, co-PI, Professor, Computer Science

    Sponsor: National Science Foundation

    Amount of Support: $130,001

    Duration of Support: 3 years

    Abstract: The proposed project will develop Visualization and Analysis of C Code Security (VACCS) tool to assist students with learning secure code programming. The proposal addresses the critical issue of learning secure coding through the development of a system for analyzing and visualizing C code and associated learning materials. VACCS will utilize static and dynamic program analysis to detect security vulnerabilities and warn programmers about the potential errors in their code. The research team has a significant experience in using visualization to teach computer science in such areas as parallel computing, geometric modeling and data encryption. The project will develop visualization and animation of common security vulnerabilities that can be customized for programmers with different level of programming experience. The project will evaluate the effectiveness of VACCS and instructional materials to improve students’ learning of secure coding.

    The outcomes of this research will provide a better understanding of the visualization impact on secure programming instruction within a computing curriculum, as well as a deployable VACCS tool for faculty to adopt. This research will inform the broader community on the visualization potential for positive effects on the quality of code developed by future computer scientists. The VACCS tool and educational materials including tutorials, lectures, projects and extensive examples of teaching secure software development will be disseminated to academic computing community. In addition, this project will teach students how to perform software security audits using VACCS and will train graduate students in the art of teaching computer security.

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    Leveraging Heterogeneous Manycore Systems for Scalable Modeling, Simulation and Verification of Nanoscale Integrated Circuits

    Researcher: Zhuo Feng, PI, Associate Professor, Electrical and Computer Engineering

    Sponsor: National Science Foundation

    Amount of Support: $400,000

    Duration of Support: 6 years

    Abstract: The goal of this CAREER research project is to best unleash the power of emerging heterogeneous manycore CPU-GPU computing platforms. This will require revolutionizing the next-generation Electronic Design Automation (EDA) tools to deal with unprecedented complexity of circuits involving billions of components, making possible their modeling, analysis and verification tasks which would be prohibitively expensive and even intractable with methods in use today. The experience acquired in this research is also likely to contribute to advances in the use of computing in other areas of science and engineering, thus impacting areas such as complex system modeling and simulation, computational fluid dynamics, social computing, and systems biology. The PI will promote undergraduate and underrepresented student research, as well as K-12 education outreach, to motivate students in pursuing advanced engineering education or a career in STEM areas. Additionally, the PI will integrate the research outcomes into undergraduate and graduate curriculum development, and leverage interdisciplinary, industrial and international collaborations to effectively facilitate the proposed research work and broadly disseminate the results. Future nanoscale Integrated Circuit (IC) subsystems, such as clock distributions, power delivery networks, embedded memory arrays, as well as analog and mixed-signal systems, may reach an unprecedented complexity involving billions of circuit components, making their modeling, analysis and verification tasks prohibitively expensive and intractable with existing EDA tools. On the other hand, emerging heterogeneous manycore computing systems, such as the manycore CPU-GPU computing platforms that integrate a few large yet power-consuming general purpose processors with massive number of much slimmer but more energy-efficient graphics processors, can theoretically delivery teraflops of computing power. The proposal aims to accelerate a paradigm shift in EDA research to more energy-efficient heterogeneous computing regimes. Towards this end, the PI will develop systematic hardware/software approaches to achieve scalable integrated circuit modeling, simulation and verifications by inventing heterogeneous CAD algorithms and data structures, as well as exploiting hardware-specific and domain-specific runtime performance modeling and optimization approaches.

    Publications:

    Xueqian Zhao*, Lengfei Han*, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

    Lengfei Han and Zhuo Feng. “Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems,” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2015.

    Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

    Lengfei Han and Zhuo Feng. “TinySPICE Plus: Scaling Up Statistical SPICE Simulations on GPU Leveraging Shared-Memory Based Sparse Matrix Solution Techniques,” IEEE/ACM International Conference on Computer-Aided Design, 2016.

    Zhuo Feng. “Spectral Graph Sparsification in Nearly-Linear Time Leveraging Efficient Spectral Perturbation Analysis,” ACM/IEEE Design Automation Conference, 2016.

    Zhiqiang Zhao, Yongyu Wang, and Zhuo Feng. “SAMG: Sparsified Algebraic Multigrid for Solving Large Symmetric Diagonally Dominant (SDD) Matrices,” IEEE/ACM International Conference on Computer-Aided Design, 2017.

    Zhiqiang Zhao, Zhuo Feng. “A Spectral Graph Sparsication Approach to Scalable Vectorless Power Grid Integrity Verication,” ACM/IEEE Design Automation Conference (DAC), 2017.

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    Graph Sparsification Approach to Scalable Parallel SPICE-Accurate Simulation of Post-layout Integrated Circuits

    Researcher: Zhuo Feng, PI, Associate Professor, Electrical and Computer Engineering

    Sponsor: National Science Foundation: SHF: Small

    Amount of Support: $250,701

    Duration of Support: 4 years

    Abstract: Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for design and verification of nanoscale ICs. However, for post-layout nanoscale circuits, using traditional SPICE-accurate simulation techniques to encapsulate multi-million or even multi-billion devices coupled through complex parasitics can be prohibitively expensive, and thus not applicable to large IC designs, since the runtime and memory cost for solving large sparse matrix problems using direct solution methods will increase quickly with the growing circuit sizes and parasitics densities. To achieve greater simulation efficiency and capacity during post-layout simulations, preconditioned iterative solution techniques have been recently proposed to substitute the direct solution methods. However, existing preconditioned methods for post-layout circuit simulations are typically designed with various assumptions and constraints on the circuit and systems to be analyzed, which therefore cannot be effectively and reliably applied to general-purpose SPICE-accurate circuit simulations. In this research project, the PI will study efficient yet robust circuit-oriented preconditioning approaches for scalable SPICE-accurate post-layout IC simulations by leveraging recent graph sparsification research. By systematically sparsifying linear/nonlinear dynamic networks originated from dense parasitics components and complex device elements of post-layout circuits, scalable, and more importantly, parallelizable preconditioned iterative algorithms will be investigated and developed by the PI to enable much greater speed and capacity for SPICE-accurate IC simulations in both time and frequency domains.

    The successful completion of this work will immediately benefit the semiconductor industries. The algorithms and methodologies to be developed through this project will be integrated into undergraduate/graduate level VLSI design/CAD courses, while the research results will be broadly disseminated to major semiconductor and EDA companies for potential industrial applications. The CAD tools developed under this research plan will also be exchanged with collaborating industrial partners. The acquired experience in the proposed research plan is also likely to contribute to computing advances in other science and engineering fields, impacting broader research areas that are related to large/complex system modeling and simulation.

    Publications:

    Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI:10.1109/TCAD.2014.2376991

    Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. doi:DOI: 10.1109/TCAD.2015.2424958

    Zhuo Feng. “Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014. doi:DOI: 10.1109/TVLSI.2013.2290104

    Xueqian Zhao, Lengfei Han, and Zhuo Feng . “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations. ,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., 2015.

    Zhuo Feng. “Spectral Graph Sparsification in Nearly-Linear Time Leveraging Efficient Spectral Perturbation Analysis,” ACM/IEEE Design Automation Conference, 2016.

    Lengfei Han, and Zhuo Feng. “Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems,” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2015.

    Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Efficient Graph Sparsification Approach to Scalable Harmonic Balance (HB) Analysis of Strongly Nonlinear RF Circuits,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013.

    Lengfei Han, Xueqian Zhao, and Zhuo Feng. “An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-layout RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

    Xueqian Zhao, Lengfei Han, and Zhuo Feng. “A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.

    Xueqian Zhao, Zhuo Feng, and Zhuo Cheng. “An Efficient Spectral Graph Sparsification Approach to Scalable Reduction of Large Flip-Chip Power Grids,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.

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    Effective Sampling-Based Miss Ratio Curves: Theory and Practice

    Circuit board

    Researcher: Zhenlin Wang, PI, Professor, Computer Science

    Sponsor: National Science Foundation

    Amount of Support: $390,876

    Duration of Support: 4 years

    Abstract: Caches, such as distributed in-memory cache for key-value store, often play a key role in overall system performance. Miss ratio curves (MRCs) that relate cache miss ratio to cache size are an effective tool for cache management. This project develops a new cache locality theory that can significantly reduce the time and space overhead of MRC construction and thus makes it suitable for online profiling. The research will influence system design in both software and hardware, as nearly every system involves multiple types of cache. The results can thus benefit a wide range of systems from personal desktops to large scale data centers. We will integrate our results into existing open source infrastructure for the industry to adopt. In addition, this project will offer new course materials that motivate core computer science research and practice.

    The project investigates a new cache locality theory, applies it to several caching or memory management systems, and examines the impact of different online random sampling techniques. The theory introduces a concept of average eviction time that facilitates modeling data movement in cache. The new model constructs MRCs with data reuse distribution that can be effectively sampled. This model yields a constant space overhead and linear time complexity. The research is focused on theoretical properties and limitations of this model when compared with other recent MRC models. With this lightweight model, the project seeks to guide hardware cache partitioning, improve memory demand prediction and management in a virtualized system, and optimize key-value memory cache allocation.

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    Combining Data and Instruction Level Parallelism through Demand Driven Execution of Imperative Programs

    Futuristic technology – Cool blue image of a computer cpu

    Researcher: Soner Onder, PI, Professor, Computer Science

    Sponsor: National Science Foundation

    Amount of Support: $113,910

    Duration of Support: 2 years

    Abstract: This project advances a new execution paradigm, namely, demand-driven execution (DDE) of imperative programs. It studies the feasibility of the paradigm by establishing theoretical performance bounds, and identifying its key scalability aspects. The primary intellectual merit of the proposal is the DDE methodology and its use in removing impediments to parallelism due to data flow and control flow. The project’s broader significance and importance stems from its impact on the design of future processors, and its synergistic use of compilers and microarchitectures. Processors built using the DDE approach can better utilize computing resources and are energy efficient.

    The basic idea behind the DDE methodology is to compile C-like programs such that both instruction-level and data-level parallelism can be used through a collaboration between compilers and microarchitectures. The basis for this collaboration is an executable, intermediate program representation known as “Future Gated Single Assignment” (FGSA) form into which a source program is compiled. The FGSA representation not only can be used by an optimizing compiler but also can be used as hardware instructions which can be directly executed by the microarchitecture.

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    Accessible Access Control

    programmer from behind and programming code on computer monitor. focus on monitor

    Researchers:

    Jean Mayo, PI, Associate Professor, Computer Science

    Ching-Kuang Shene, co-PI, Professor, Computer Science

    Steven Carr, co-PI, Adjunct, Computer Science, Michigan Technological University

    Chaoli Wang, co-PI

    Sponsor: National Science Foundation

    Amount of Support: $199,164

    Duration of Support: 3 years

    Abstract: Access control is a last line of defense for protecting computer system resources from a compromised process. This is a primary motivation for the principle of least privilege, which requires that a process be given access to only those resources it needs in order to complete its task. Enforcement of this principle is difficult. A strict access control policy can contain tens of thousands of rules, while errors in the policy can interrupt service and put system resources at risk unnecessarily. This project is developing materials that facilitate education on modern access control models and systems. A policy development system leverages visualization to enhance student learning. The policy development system allows graphical development and analysis of access control policies. It runs at the user-level, so that student work does not impact operation of the underlying system and so that access to a specific operating system is not required. A set of web-based tutorials is being developed that are suitable for study out of the classroom. The project results will increase the number of institutions that offer deep coverage of access control in their curriculum and will facilitate development of the relevant expertise by workers who are not able to pursue formal education. Computer system security breaches cost companies billions of dollars per year. By helping to create a workforce trained to use modern access control systems effectively, this project increases the ability of industry to protect electronic data.

    Publications: Carr, Steve and Mayo, Jean. “Workshop on Teaching Modern Models of Access Control Hands-on: Tutorial Presentation,” J. Comput. Sci. Coll., v.32, 2016, p. 35–36. doi:1937-4771

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    Multistatic GPR for Explosive Hazards Detection (Phase I & II)

    Researcher: Timothy Havens, PI, William and Gloria Jackson Associate Professor of Computer Systems, and Director, Institute of Computing and Cybersystems

    Sponsor: Akela, Inc. / U.S. Army

    Amount of Support: $83,359

    Abstract: In this project researchers examine how unmanned aerial vehicles and terrestrial GPR can coordinate to improve buried explosive hazard detection performance.


    National University Rail (NURail) Center – Tier I

    Researchers:

    Pasi Lautala, PI, Associate Professor, Civil and Environmental Engineering, and Director, Rail Transportation Program, Michigan Tech Transportation Institute

    Timothy Havens, Co-PI, William and Gloria Jackson Associate Professor of Computer Systems, and Director, Institute of Computing and Cybersystems

    Philart Jeon, Co-PI, Adjunct Associate Professor, Computer Science and CLS

    Paul Sanders, Co-PI, Patrick Horvath Endowed Professor of Materials Science and Engineering

    Sponsor: US Department of Transportation / RITA

    Amount of Support: $299,966

    Abstract: The National University Rail (NURail) Center is a consortium of seven partner colleges and universities offering an unparalleled combination of strengths in railway transportation engineering research and education in North America. The NURail Center is the first USDOT OST-R University Transportation Center dedicated to the advancement of North American rail transportation. The Center is headquartered at the University of Illinois at Urbana-Champaign and includes researchers and educators who are experts and national leaders in railway infrastructure, systems and vehicles from seven prestigious academic institutions in the United States.


    Implementation of Unmanned Aerial Vehicles (UAVs) for Assessment of Transportation Infrastructure

    Copter flight against the blue sky. RC aerial drone.

    Researchers:

    Colin Brooks, PI, PhD Student, Biological Sciences

    Timothy Havens, Co-PI, William and Gloria Jackson Associate Professor of Computer Systems

    Kuilin Zhang, Co-PI, Assistant Professor, Civil and Environmental Engineering

    Richard Dobson, Co-PI

    Tess Ahlborn, Co-PI, Professor, Civil and Environmental Engineering

    A. Mukherjee, Co-PI, Associate Professor, Civil and Environmental Engineering

    Sponsor: Michigan Dept. Transportation (MDOT)

    Amount of Support: $598,526

    Abstract: As unmanned aerial vehicle (UAV) technology has advanced to become more capable at lower cost, it offers transportation agencies a more rapid and safer alternative to collect data for a variety of applications, including condition assessment, traffic monitoring, construction, asset management, operations, and other applications. Through successful research, development, and demonstrations during Phase 1 of this project, the Michigan Tech team was able to test multiple sensors on a Michigan-made multirotor UAV platform, along with other UAVs, enabling the collection of data types such as optical light detection and ranging (LiDAR) and thermal to achieve a detailed view of a bridge deck both on the surface and subsurface. These methods were developed to represent the type of data collected through Michigan Department of Transportation (MDOT) manual inspections. Further development of UAV technology for the use of transportation infrastructure assessment is required in order to fully implement these technologies into MDOT day-to-day operations. By successfully continuing UAV research and development for MDOT, the Michigan Tech team will produce practical applications of large datasets that will support MDOT’s business models and decision making processes.