Yuchen Wang to Present Ph.D. Dissertation Proposal March 31

Department of Computer Science graduate student Yuchen Wang will present his Ph.D. dissertation proposal on Friday, March 31, 2023, from 4-5 p.m., in Rekhi Hall, Room 101, and virtually.

The title of Wang’s presentation is, “Dynamic Memory Management for Key-Value Stores.” Wang is advised by Professor Zhenlin Wang, Computer Science department.

Proposal Abstract: To reduce the latency of accessing back-end servers, today’s web services usually adopt in-memory key-value stores in the front end which cache the frequently accessed objects. Due to the limited size of memory, an in-memory key-value store needs to be configured with a fixed amount of memory, i.e., cache size, and cache replacement is unavoidable when the footprint of accessed objects is larger than the cache size. Redis adopts an approximated LRU policy based on K randomly sampled keys (K-LRU), to avoid maintaining LRU list structures, where we find that K-LRU behaves close to LRU when K is large. This cache replacement scheme shows great potential in key-value store memory management.

With the emergence of new shared memory technologies such as Compute Express Link (CXL), it is potential for in-memory key-value stores to use this new technology in a tiered memory environment to improve system performance at less cost. The tiered memory system integrates fast memory such as local DRAM and slow memories provided by CXL as an efficient huge memory pool to facilitate services such as application accelerating and database offload.

This proposal surveys the literature and introduces two preliminary works. The first one conducted a detailed analysis of K-LRU behavior and proposed a dynamic K configuring scheme in Redis to explore the potential miss ratio gap among various Ks. Results showed up to a 32.5% throughput improvement over the default static K setting.

The second work pushed K-LRU exploration forward to a multi-tenant key-value store environment and proposed a locality-and latency-aware memory partitioning scheme to meet adjustable optimization objectives. It delivered up to a 50.2% average access latency reduction, and up to a 262.8% throughput improvement compared to Redis. Furthermore, by comparing against a state-of-the-art design of memory allocation, it showed up to 24.8% and 61.8% improvements in average access latency and throughput, respectively.

Drawing inspiration from preliminary works and emerging CXL-enabled memory-sharing techniques, we propose new contributions to the tiered memory management of key-value stores: the design of a new tiered memory management architecture on top of CXL memory-sharing switch; locality- and latency-aware multi-tenant memory partitioning of tiered memory; efficient application-level data placement and migration among memory tiers based on item popularity tracking and random sampling inspired by K-LRU policy.