Institute of Computing and Cybersystems (ICC) Blog

Author: Karen Johnson

The Michigan Tech College of Computing offers a full range of undergraduate and graduate degrees in the Computing disciplines.

Dr. Theda Daniels-Race to Present Seminar September 9

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Dr. Theda Daniels-Race, the Michael B. Voorheis Distinguished Professor in the Division of Electrical & Computer Engineering at Louisiana State University, will present her seminar, “Deposition, Characterization, and Developments in Hybrid Electronic Materials for Next-Generation Nanoelectronics,” on Monday, September 9, at 3:00 pm in Room 6452 of the Dow Environmental Sciences and Engineering Building.

This seminar is presented by the Institute of Computing and Cybersystems and the Michigan Tech Visiting Professor Program, which is funded by a grant to the Michigan Tech Provost Office from the State of Michigan’s King-Chavez-Parks Initiative.

Dr. Daniels-Race also has a  joint appointment to the Center for Computation and Technology at Louisiana State University.  She is the founder of the Applied Hybrid Electronic Materials & Structures Laboratory as well as Director of the ECE Division’s Electronic Materials & Devices Laboratory.  Her research has encompassed a range of studies upon electronic materials from the growth of compound semiconductors via molecular beam epitaxy (MBE), to investigations of electron transport in low-dimensional systems such as quantum wells, wires, and dots, to device design and fabrication.  Her current work is in the area of hybrid electronic materials (HEMs) and involves studies of sample morphologies, nanoscale electronic behavior, and the design of apparatus for HEM deposition.

Dr. Daniels-Race received her degrees in Electrical Engineering from Rice, Stanford, and Cornell universities, for the B.S., M.S., and Ph.D., respectively.  As an undergraduate, she received a GEM (Graduate Engineering Minorities) Fellowship for her future MS studies, and while working on her masters, she was selected to receive one of fewer than ten CRFP (Cooperative Research Fellowship Program) competitive fellowships awarded nationally that year by AT&T for her PhD. Throughout her academic training, Daniels-Race worked in industry with corporations such as Union Carbide, Exxon, General Electric, and AT&T Bell Laboratories.  She began her academic career with the ECE Department at Duke University, where she built that institution’s first MBE laboratory and, over the next thirteen years, established a program in experimental compound semiconductor materials research.  Daniels-Race was recruited to join the LSU faculty where she conducts research upon HEMs for use in next-generation nanoscale devices.  To the community she has been an active member of several professional societies including the IEEE, the American Physical Society, the Materials Research Society, and the National Society of Black Physicists.  She is an ELATES (Executive Leadership in Academic Technology, Engineering and Science) alumna and is a strong advocate for minorities and women in science and engineering.

Seminar Abstract: Ubiquitous dependence upon semiconductor-based technology has reached a critical turning point.  In effect “small has hit the wall” (Moore’s Law) as advancements, in everything from cell phones to satellites, struggle to keep pace with demands for smaller, faster, and ever more affordable devices. Thus, researchers operating under the broadly defined umbrella of nanoelectronics inherently challenge traditional solid-state electronic design paradigms and fabrication practices.  To this end, my research focuses upon that which I have dubbed HEMs or “hybrid electronic materials.”  In this talk, I will present an overview of work in progress, conducted by both my graduate and undergraduate students, as part of the Applied Hybrid Electronic Materials & Structures (AHEMS) Laboratory that I have established in the Division of Electrical and Computer Engineering at Louisiana State University. With an eye toward the next generation of electronics, new materials and nanoscale structures must be investigated in order to understand the unique physics and potential applications of electronic phenomena “beyond the transistor.”  Using hybrid (inorganic-organic) electronic materials, my group works to characterize the nanoscale formations and electronic behavior of HEMs, as well as to develop innovative yet low-cost apparatus and techniques through which these materials may be explored.

Theda Daniels-Race CV

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GenCyber Camp for Teachers Garners Local Media Coverage

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Michigan Tech hosted two week-long GenCyber camps this summer. The first, held June 17–21, 2019, hosted 30 local middle/high school students. The second camp, August 12–16, 2019, hosted 21 local K-12 teachers. Camp participants gained cybersecurity knowledge, understood correct and safe online behavior, and explored ways to deliver cybersecurity content in K-12 curricula.

A story about the GenCyber teacher camp was reported on August 16, 2019, by TV6: “GenCyber cyber security training camp comes to Michigan Tech” and on August 13, 2019, by the Keweenaw Report: “Teachers Learn How To Include Cybersecurity In Their Lessons.”

Learn more about the camps on the Institute of Computing and Cybersystems blog: https://blogs.mtu.edu/icc/2019/06/04/inspiring-the-next-generation-of-cyber-stars-2/.

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Soner Onder Presents Keynote at SAMOS XIX

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Soner Onder
Soner Onder

Soner Onder (SAS), professor of computer science, presented a keynote lecture July 8, 2019, at the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIX) on Samos Island, Greece, which was held July 7-11. Onder’s talk was titled, “Form Follows Function: The Case for Homogeneous Computer Architectures.” Onder also participated in the conference’s “The Annual Open Mike Panel.”

Keynote Lecture Abstract: ”Form follows function” is a principle associated with 20th-century modernist architecture and industrial design which says that the shape of a building or object should primarily relate to its intended function or purpose”[2]. For best performance in computer architecture, form must follow function as well. What are form and function in computer architecture? Form is easy to understand and interpret in its dictionary meaning; Function is not so clear-cut. In this talk, I will start with a simple problem, an algorithm, and a basic program representation that will be interpreted by the machine, and show that delivering high performance rests on solving only a handful, but fundamentally difficult problems. I will argue that the mere existence of domain specific solutions that general purpose computing cannot match in performance is a testament that the general purpose computing is ”not general enough”. What makes an architecture ”not general enough” is not the architecture itself, but rather the mismatch between the function its form had followed and the actual semantics of programs. To illustrate the point, I will challenge the widely understood interpretation of instruction-level parallelism (ILP) as ”single-thread performance”, and show that this interpretation is too short-sighted. We can efficiently exploit all types of available parallelism, including process-level, thread-level and data level parallelism, all at the instruction-level, and this approach is both feasible and necessary to combat the complexity that is plaguing our profession. I will then discuss why an executable single-assignment program representation [1] may be the ultimate function whose implementations may result in homogeneous general purpose architectures that can potentially match the performance of accelerators for specific tasks, while exceeding the performance of any accelerator traditional architecture combination for general tasks. I will conclude by discussing our results with Demand-driven Execution (DDE), whose form follows this single-assignment program representation.

About SAMOS (from http://samos-conference.com/): SAMOS is a unique conference. It deals with embedded systems (sort of) but that is not what makes it different. It brings together every year researchers from both academia and industry on the quiet and inspiring northern mountainside of the Mediterranean island of Samos, which in itself is different. But more importantly, it really fosters collaboration rather than competition. Formal and intensive technical sessions are only held in the mornings.A lively panel or distinguished keynote speaker ends the formal part of the day, and leads nicely into the afternoons and evenings — reserved for informal discussions, good food, and the inviting Aegean Sea. The conference papers will be published by Springer’s Lecture Notes in Computer Science – LNCS and will be included in the DBLP Database.

Samos Island, Greece
Samos Island, Greece
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Soner Onder Presents Talk in Barcelona, Spain

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Soner Onder is pictured on the right in the front.

Sonder Onder (SAS), professor of computer science, presented an invited talk at “Yale:80: Pushing the Envelope of Computing for the Future,” held July 1-2, 2019, in Barcelona, Spain. The workshop was organized by Universitat Politècnica de Catalunya in honor of the 80th birthday of Yale Patt, a prominent computer architecture researcher. Onder was one of 23 invitees to give a talk. His lecture was titled, “Program semantics meets architecture: What if we did not have branches?”

View the slides from Onder’s talk: Yale80-in-2019-Soner-Onder

Yale Patt is a professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin, where he holds the Ernest Cockrell, Jr. Centennial Chair in Engineering. He also holds the title of University Distinguished Teaching Professor. Patt was elected to the National Academy of Engineering in 2014, among the highest professional distinctions bestowed upon an engineer. View Patt’s faculty webpage at: http://www.ece.utexas.edu/people/faculty/yale-patt.

Link to the workshop’s website here: http://research.ac.upc.edu/80-in-2019/

Visit the workshop’s Facebook page here: https://www.facebook.com/BSCCNS/posts/workshop-yale-80-in-2019pushing-the-envelope-of-computing-for-the-futurehttprese/2217508564992996/

Soner Onder, Barcelona, Spain
Soner Onder at Sagrada Família, Barcelona, Spain
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Benjamin Ong Awarded 25K for Parallel-in-time Integration Workshop

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Benjamin Ong

Benjamin Ong (Math/ICC-DataS) is Principal Investigator on a one-year project that has received a $25,185 other sponsored activities grant from the National Science Foundation. The project is titled “Ninth Workshop on Parallel-In-Time Integration.”

The Ninth Workshop on Parallel-in-time Integration will take place June 8 – 12, 2020, at Michigan Tech. Ong (chair) and Jacob Schroder, assistant professor in the Dept. of Mathematics and Statistics at University of New Mexico, are heading the organizing committee for the workshop. Travel funding for early career researchers will be available. Application details and deadlines will be posted shortly on the event’s website at conferences.math.mtu.

Contact information:
ongbw@mtu.edu
906-487-3367

Invited speakers:

  • Professor Matthias Bolten, Bergische Universität Wuppertal
  • Professor Laurence Halpern, Université Paris 13
  • Professor George Karniadakis, Brown University
  • Professor Ulrich Langer, Johannes Kepler University Linz
  • Dr. Carol Woodward, Lawrence Livermore National Laboratory

The workshop is supported by:

  • Michigan Technological University, Department of Mathematical Sciences
  • Michigan Technological University, College of Science and Arts
  • Lawrence Livermore National Laboratory
  • Jülich Supercomputing Centre
  • FoMICS: The Swiss Graduate School in Computational Science

About the Workshop on Parallel-in-time Integration (from https://parallel-in-time.org/ and https://parallel-in-time.org/events/9th-pint-workshop/)

Computer models and simulations play a central role in the study of complex systems in engineering, life sciences, medicine, chemistry, and physics. Utilizing modern supercomputers to run models and simulations allows for experimentation in virtual laboratories, thus saving both time and resources. Although the next generation of supercomputers will contain an unprecedented number of processors, this will not automatically increase the speed of running simulations. New mathematical algorithms are needed that can fully harness the processing potential of these new systems. Parallel-in-time methods, the subject of this workshop, are timely and necessary, as they extend existing computer models to these next generation machines by adding a new dimension of scalability. Thus, the use of parallel-in-time methods will provide dramatically faster simulations in many important areas, such as biomedical applications (e.g., heart modeling), computational fluid dynamics (e.g., aerodynamics and weather prediction), and machine learning. Computational and applied mathematics plays a foundational role in this projected advancement.

The primary focus of the proposed parallel-in-time workshop is to disseminate cutting-edge research and facilitate scientific discussions on the field of parallel time integration methods. This workshop aligns with the National Strategic Computing Initiative (NCSI) objective: “increase coherence between technology for modeling/simulation and data analytics”. The need for parallel time integration is being driven by microprocessor trends, where future speedups for computational simulations will come through using increasing numbers of cores and not through faster clock speeds. Thus as spatial parallelism techniques saturate, parallelization in the time direction offers the best avenue for leveraging next generation supercomputers with billions of processors. Regarding the mathematical treatment of parallel time integrators, one must use advanced methodologies from the theory of partial differential equations in a functional analytic setting, numerical discretization and integration, convergence analyses of iterative methods, and the development and implementation of new parallel algorithms. Thus, the workshop will bring together an interdisciplinary group of experts spanning these areas.

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Michigan Ag News Headlines: Found in Translation at Michigan Tech

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James Bialas does an aerial drone demonstration for students attending the Surveying Summer Youth Program exploration at Michigan Technological University. Drones are one tool in the remote sensing arsenal. Image Credit: Peter Zhu

Research conducted by Michigan Tech doctoral candidate James Bialas and faculty members Thomas Oommen (DataS/GMES/CEE) and Timothy Havens (DataS/CS) made news in the Michigan Ag Connection, August 7, 2019. The item is a re-posting of the Michigan Tech Unscripted article, “Found in Translation, which was posted on the Michigan Tech website July 12, 2019.

http://michiganagconnection.com/story-state.php?Id=856&yr=2019

https://www.mtu.edu/news/stories/2019/july/found-in-translation.html

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Ali Ebnenasir is Co-author of Article in ACM Transactions on Computational Logic

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Ali EbnenasirAli Ebnenasir (SAS/CS), professor of computer science, is co-author of the article, “On the verification of livelock-freedom and self-stabilization on parameterized rings,” published in the July 2019 issue of the journal ACM Transactions on Computational Logic. The article is co-authored by Alex Klinkhamer of Google.

Abstract: This article investigates the verification of livelock-freedom and self-stabilization on parameterized rings consisting of symmetric, constant space, deterministic, and self-disabling processes. The results of this article have a significant impact on several fields, including scalable distributed systems, resilient and self-* systems, and verification of parameterized systems. First, we identify necessary and sufficient local conditions for the existence of global livelocks in parameterized unidirectional rings with unbounded (but finite) number of processes under the interleaving semantics. Using a reduction from the periodic domino problem, we show that, in general, verifying livelock-freedom of parameterized unidirectional rings is undecidable (specifically, Π10-complete) even for constant space, deterministic, and self-disabling processes. This result implies that verifying self-stabilization for parameterized rings of self-disabling processes is also undecidable. We also show that verifying livelock-freedom and self-stabilization remain undecidable under (1) synchronous execution semantics, (2) the FIFO consistency model, and (3) any scheduling policy. We then present a new scope-based method for detecting and constructing livelocks in parameterized rings. The proposed semi-algorithm behind our scope-based verification is based on a novel paradigm for the detection of livelocks that totally circumvents state space exploration. Our experimental results on an implementation of the proposed semi-algorithm are very promising as we have found livelocks in parameterized rings in a few microseconds on a regular laptop. The results of this article have significant implications for scalable distributed systems with cyclic topologies.

Citation: Klinkhamer, A., & Ebnenasir, A. (2019). On the verification of livelock-freedom and self-stabilization on parameterized rings. ACM Transactions on Computational Logic, 20(3), 16:1-16:36. http://dx.doi.org/10.1145/3326456

MTU Digital Commons link: https://digitalcommons.mtu.edu/michigantech-p/146/

ACM link: https://dl.acm.org/citation.cfm?doid=3338853.3326456

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Saeid Nooshabadi is Co-author of Article in Journal of Parallel and Distributed Computing

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Saeid Nooshabadi

Saeid Nooshabadi (SAS/ECE), professor of electrical and computer engineering, is co-author of the article, “High-dimensional image descriptor matching using highly parallel KD-tree construction and approximate nearest neighbor search,” to be published in  the October 2019 issue of the Journal of Parallel and Distributed Computing, which is published by Elsevier. The article is co-authored by Michigan Tech Computer Science department doctoral candidate Linjia Hu.

Abstract: To overcome the high computational cost associated with the high-dimensional digital image descriptor matching, this paper presents a set of integrated parallel algorithms for the construction of K-dimensional tree (KD-tree) and P approximate nearest neighbor search (P-ANNS) on the modern massively parallel architectures (MPA). To improve the runtime performance of the P-ANNS, we propose an efficient sliding window for a parallel buffered P-ANNS on KD-tree to mitigate the high cost of global memory accesses. When applied to high dimensional real-world image descriptor datasets, the proposed KD-tree construction and the buffered P-ANNS algorithms are of comparable matching quality to the traditional sequential counterparts on CPU, while outperforming their serial CPU counterparts by speedup factors of up to 17 and 163, respectively. The algorithms are also studied for the performance impact factors to obtain the optimal runtime configurations for various datasets. Moreover, we verify the features of the parallel algorithms on typical 3D image matching scenarios. With the classical local image descriptor signature of histograms of orientations (SHOT) datasets, the parallel KD-tree construction and image descriptor matching can achieve up to 11 and 138-fold speedups, respectively.

Citation: Hu, L., & Nooshabadi, S. (2019). High-dimensional image descriptor matching using highly parallel KD-tree construction and approximate nearest neighbor search. Journal of Parallel and Distributed Computing, 132, 127-140. http://dx.doi.org/10.1016/j.jpdc.2019.06.003

MTU Digital Commons link: https://digitalcommons.mtu.edu/michigantech-p/145/

Elsevier link: https://www.sciencedirect.com/science/article/pii/S0743731519304319?via%3Dihub

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Zhenlin Wang is Co-Author of Article in Parallel Programming Journal

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Zhenlin Wang (SAS), professor of computer science, is co-author of the article, “Lightweight and accurate memory allocation in key-value cache,” published in the June 2019 issue of the International Journal of Parallel Programming, which is published by Springer.

Abstract: The use of key-value caches in modern web servers is becoming more and more ubiquitous. Representatively, Memcached as a widely used key-value cache system, originally intended for speeding up dynamic web applications by alleviating database load. One of the key factors affecting the performance of Memcached is the memory allocation among different item classes. How to obtain the most efficient partitioning scheme with low time and space consumption is a focus of attention. In this paper, we propose a lightweight and accurate memory allocation scheme in Memcached, by sampling access patterns, analyzing data locality, and reassigning the memory space. One early study on optimizing memory allocation is LAMA, which uses footprint-based MRC to optimize memory allocation in Memcached. However, LAMA does not model deletion operations in Memcached and its spatial overhead is quite large. We propose a method that consumes only 3% of LAMA space and can handle read, write and deletion operations. Moreover, evaluation results show that the average stable-state miss ratio is reduced by 15.0% and the average stable-state response time is reduced by 12.3% when comparing our method to LAMA.

Citation: Pan, C., Zhou, L., Luo, Y., Wang, X., & Wang, Z. (2019). Lightweight and accurate memory allocation in key-value cache. International Journal of Parallel Programming, 47(3), 451-466.http://dx.doi.org/10.1007/s10766-018-0616-4

Digital Commons link: https://digitalcommons.mtu.edu/michigantech-p/144/

Springer link: https://link.springer.com/article/10.1007%2Fs10766-018-0616-4

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